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asahi kasei [AK61584] 0185-e-00 ?98/04 -1- AK61584 dual low power t1/e1 line interface features - provides dual analog pcm line interface for short-haul,t1 and e1 applications - jitter tolerance: compliant with at&t62411 tr-nwt-000499 category i ,ii itu-t g.823 - transmitter pulse shape: compliant with at&t62411,cb119, tr-nwt-000499, itu-t g.703 - jitter transfer: at&t62411, itu-t g.736 - operating mode fully software configur able. no external quartz crystal is required. - support of j tag boundary scan - low power consumption - 3.3volt op eration - small plastic package 64pin lqfp( 10*10* 1.4mm ) general description the AK61584 is a universal line interface for t1/e1 applica- tions, designed for high-volume cards where low power, high density and universal operation is required. one board design can support all t1/e1 modes. the AK61584 is a low-power cmos device available in 3.3 volt. preliminary product information this document contains information for a new product. akm reserves the right to modify this product without notice. tclk1 ( tdata1)tpos1 hardware mode rloop2atten0atten1rloop1lloop1lloop2taos1taos2 con01 con02 con11 con12 con21 con22 coder1 coder2 clke serial port ipol (note) cs int sclk sdo sdi spol control control jtag clock generator jitter attenuator jitter attenuator taos taos detect los& ais los& ais detect pulse shaping circuitry pulse shaping circuitry clock& data recovery clock& data recovery driver driver remote loopback encoder decorder local loopback1 local loopback2 4 2 2 22 3 refclk 1xclk tv+ tgnd rv+ rgnd dv+ dgnd av+ agnd bgref pd1 pd2 los1 los2 (ais1)tneg1 rclk1 ( rdata1)rpos1 (bpv1)rneg1 tclk2 ( tdata2)tpos2 (ais2)tneg2 rclk2 ( rdata2)rpos2 (bpv2)rneg2 ttip1 tring1 rtip1 rring1 ttip2 tring2 rtip2 rring2 reset mode note) in host mode, this pin must be tied to gnd. encoder decorder remote loopback local loopback1 loc al loo pbac k2
asahi kasei [AK61584] 0185-e-00 ?98/04 -2- table of contents block diagram ................................................................................ 1 specifications absolute maximum ratings ............................................ 3 recommended operating conditions .............................. 3 digital characteristics ..................................................... 4 analog specifications receiver .............................................................. 4 jitter attenuator .................................................. 4 transmitter ......................................................... 5 switching characteristics t1 clock/data .................................................... 6 e1 clock/data .................................................... 6 serial port ........................................................... 8 jtag .................................................................. 9 general description overview ........................................................................10 operating options ..........................................................11 overview of applications ...............................................12 transmitter .....................................................................13 receiver .........................................................................15 jitter attenuator..............................................................16 coder mode ...................................................................17 reference clock.............................................................17 loopbacks ......................................................................17 power down ..................................................................17 reset ..............................................................................18 power-on reset .............................................................18 control...........................................................................18 registers ........................................................................21 host-mode register access ...........................................23 arbitrary waveform generation .....................................24 power supply .................................................................24 jtag boundary scan .....................................................24 pin description ..............................................................................32
asahi kasei [AK61584] 0185-e-00 ?98/04 -3- absolute maximum ratings parameter symbol min max units dc supply(tv+1,tv+2,rv+1,rv+2,av+,dv+)(note 1) - 6.0 v input voltage any pin vin rgnd-0.3 (rv+)+0.3 v input current any pin (note 2) iin -10 10 ma ambient operating temperature ta -40 85 o c storage temperature tstg -65 150 o c warning: operations at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. notes: 1. referenced to rgnd1,rgnd2,tgnd1,tgnd2,agnd,dgnd at 0v. 2. transient currents of up to 100 ma will not cause scr latch-up. recommended oper ating conditions parameter symbol min typ max units dc supply(tv+1,tv+2,rv+1,rv+2,av+,dv+) (note 3) 3.135 3.3 3.465 v ambient operating temperature ta -40 25 85 o c power consumption t1 (notes 4 and 5) (each channel) t1 (notes 4 and 6) e1,75ohm (notes 4 and 5) e1,120ohm (notes 4 and 5) pc - - - - 292 167 180 170 380 220 210 200 mw mw mw mw refclk frequency t1 1xclk=1 1.544- 100ppm 1.544 1.544+ 100ppm mhz t1 1xclk=0 12.352- 100ppm 12.352 12.352+ 100ppm mhz e1 1xclk=1 2.048- 100ppm 2.048 2.048+ 100ppm mhz e1 1xclk=0 16.384- 100ppm 16.384 16.384+ 100ppm mhz notes: 3. tv+1,tv+2,av+,dv+,rv+1,rv+2 should be connected together.tgnd1,tgnd2,rgnd1, rgnd2,dgnd1,dgnd2,dgnd3 should be connected together. 4. power consumption while driving line load over operating temperature range. lncludes ic and load. digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pf capacitive load. 5. assumes 100% ones density and maximum line length at 3.465v. 6. assumes 50% ones density and 300ft. line length at 3.3v.
asahi kasei [AK61584] 0185-e-00 ?98/04 -4- digital characteristics (t a =-40 to 85 o c;power supply pins within +/-5% of nominal) parameter symbol min typ max units high-level input voltage (note 7) v ih (dv+)-0.5 - - v low-level input voltage (note 7) v il - - 0.5 v high-level output voltage (note 8) iout=-40ua v oh (dv+)-0.3 - - v low-level output voltage (note 8) iout=1.6ma v ol - - 0.4 v input leakage current (digital pins except int, j_tms, and j_tdi) - - +/-10 ua notes: 7. digital inputs are designed for cmos logic levels. 8. digital outputs are ttl compatible and drive cmos levels into a cmos load. analog specific ations (t a =-40 to 85 o c;power supply pins within +/-5% of nominal) parameter min typ max units receiver input impedance between rtip/rring - 20k - ohm sensitivity below dsx-1(0 db=2.4v) -13.6 - - db loss of signal threshold, short haul t1 e1 - - 0.23 0.15 - - v 0p v 0p data decision threshold t1,dsx-1 (note 9) (note 10) e1 (note 11) (note 12) 60 55 45 40 65 - 50 - 70 75 55 60 % of peak allowable consecutive zeros before los 160 175 190 bits receiver input jitter 10 hz and below (note 13) tolerance(dsx-1,e1) 2 khz 10 khz-100 khz 300 6.0 0.4 - - - - - - ui pp ui pp ui pp jitter attenuator jitter attenuation curve corner frequency (note 14 and 15) t1 e1 - - 4 5.5 - - hz hz attenuation at 10 khz jitter frequency (note 14 and 15) - 60 - db attenuator input jitter tolerance (note 14) (before onset of fifo overflow or underflow protection) 28 43 - ui pp notes: 9. for input amplitude of 1.2vpk to 4.14vpk 10. for input amplitude of 0.5vpk to 1.2vpk, and 4.14vpk to 5.0vpk 11. for input amplitude of 1.07vpk to 4.14vpk 12. for input amplitude of 4.14vpk to 5.0vpk 13. jitter tolerance increases at lower frequencies. see figure 11. 14. not production tested. parameters guaranteed by design and characterization. 15. attenuation measured with sinusoidal input jitter equal to 3/4 of measured jitter tolerance. circuit attenuates jitter at 20 db/decade above the corner frequency. see figure 16. output jitter can increase significantly when more than 28 uis are input to the attenuator. see discussion in jitter attenuator section.
asahi kasei [AK61584] 0185-e-00 ?98/04 -5- analog specific ations (t a =-40 to 85 o c;power supply pins within +/-5% of nominal) parameter min typ max units transmitter ami output pulse amplitudes (note 16) e1,75ohm (note 17) e1,120ohm (note 18) t1,dsx-1 (note 19) 2.14 2.7 2.4 2.37 3.0 3.0 2.6 3.3 3.6 v 0p v 0p v 0p recommended transmitter output load (note 16) t1, e1,75ohm e1,120ohm - - - 25 43 68.9 - - - ohm ohm ohm jitter added by the transmitter 8khz C 40khz 10hz C 40khz broad band (note 20) - - - 0.013 0.016 0.027 - - - ui pp ui pp ui pp power in 2 khz band about 772 khz (notes 14 and 21) (dsx-1 only) 12.6 15 17.9 dbm power in 2 khz band about 1.544 mhz (notes 14 and 21) (referenced to power in 2 khz band at 772 khz) (dsx-1 only) -29 -38 - db positive to negative pulse imbalance (notes 14 and 21) t1,dsx-1 e1,amplitude at center of pulse interval e1,width at 50% of nominal amplitude - -5 -5 0.2 - - 0.5 +5 +5 db % % transmitter return loss (notes 14, 21, and 22) 51 khz - 102 khz 102 khz - 2.048 mhz 2.048 mhz - 3.072 mhz 8 14 10 - - - - - - db db db e1 short circuit current (note 23) - - 50 marms e1 and dsx-1 output pulse rise/fall times (note 24) - 25 - ns e1 pulse width (at 50% of peak amplitude) - 244 - ns e1 pulse amplitude e1, 75ohm for a space e1,120ohm -0.237 -0.3 - - 0.237 0.3 v 0p v 0p notes: 16. using a transformer that meets the specifications in table 2. 17. measured across 75ohm at the output of the transmit transformer for con2/1/0=0/0/0. 18. measured across 120ohm at the output of the transmit transformer for con2/1/0=0/0/1. 19. measured at the dsx-1 cross-connect for line length settings con2/1/0=0/1/0, 0/1/1, 1/0/0, 1/0/1, and 1/1/0 after the length of #22 abam cable specified in table 1. 20. input signal to tclk is jitter free. 21. typical performance with a 0.47 uf capacitor in series with primary of transmitter output transformer. 22. return loss = 20 log 10 abs ((z1+z0)/(z1-z0)) where z1 = impedance of the transmitter, and z 0 =cable impedance. 23. transformer secondaries shorted with 0.5ohm resistor. 24. at transformer secondary. from 10% to 90% of amplitude.
asahi kasei [AK61584] 0185-e-00 ?98/04 -6- switching characteristics-t1 clock/ data (t a = -40 to 85 o c;power supply pins within +/-5% of nominal; inputs: logic 0=0v, logic 1=dv+)(see figures 1,2, and 3) parameter symbol min typ max units tclk frequency (note 25) f tclk - 1.544 - mhz tclk duty cycle t pwh2 /t pw2 30 50 70 % rclk duty cycle (note 26) t pwh1 /t pw1 45 50 55 % rise time all digital outputs (note 27) t r --65ns fall time all digital outputs (note 27) t r --65ns tpos/tneg to tclk falling setup time t su2 25 - - ns tclk falling to tpos/tneg hold time t h2 25 - - ns rpos/rneg to rclk rising setup time t su1 - 274 - ns rclk rising to rpos/rneg hold time t h1 - 274 - ns notes: 25. max value of 8.192 mhz describes the maximum burst rate of a gapped input clock(tclk). for the gapped clock to be tolerated by the AK61584, the jitter attenuator must be switched to transmit path of the line interface. the maximum gap size is defined in the analog specification table. 26. rclk duty cycle may be outside the spec limits when jitter attenuator is in the receive path, and when the jitter attenuator is employing the overflow/underflow protection mechanism. 27. at max load of 50pf. switching characteristics-e1 clock/ data (t a = -40 to 85 o c;power supply pins within +/-5% of nominal; inputs: logic 0=0v, logic 1=dv+)(see figures 1, 2, and 3) parameter symbol min typ max units tclk frequency (note 25) f tclk - 2.048 - mhz tclk duty cycle t pwh2 /t pw2 30 50 70 % rclk duty cycle (note 26) t pwh 1/t pw1 45 50 55 % rise time all digital outputs (note 27) t r --65ns fall time all digital outputs (note 27) t r --65ns tops/tneg to tclk falling setup time t su2 25 - - ns tclk falling to tops/tneg hold time t h2 25 - - ns rpos/rneg to rclk rising setup time t su1 - 194 - ns rclk rising to rpos/rneg hold time t h1 - 194 - ns
asahi kasei [AK61584] 0185-e-00 ?98/04 -7- any digital output tr tf figure 1. signal rise and fall characteristics 10% 90% 90% 10% tpw1 tpwl1 tpwh1 tsu1 th1 rclk (for clke=high) rpos rneg rclk (for clke=low) figure 2. recoverd clock and data switching characteristics tpw2 tpwh2 tsu2 th2 tclk tpos/tneg figure 3. transmit clock and data switching characteristics (rdata) (tdata)
asahi kasei [AK61584] 0185-e-00 ?98/04 -8- switching characteristics - serial port (t a = -40 to 85 o c; dv+,tv+,rv+ = nominal +/- 0.3v; inputs: logic 0 = 0v, logic 1 = rv+) parameter symbol min typ max units sdi to sclk setup time t dc 25 - - ns sclk to sdi hold time t cdh 25 - - ns sclk low time t cl 50 - - ns sclk high time t cl 50 - - ns sclk rise and fall time t r ,t f --15ns cs to sclk setup time t cc 20 - - ns sclk to cs hold time (note 28) t cch 20 - - ns cs inactive time t cwh 100 - - ns sclk to sdo valid (note 29) t cdv --50ns cs to sdo high z t cdz -50-ns notes: 28. if spol=0, then cs should return high no sooner than 20ns after the 16th falling edge of sclk during a serial port read. 29. output load capacitance = 50 pf. cs sclk sdi lsb lsb msb control byte data byte tcwh tcch tcc tch tcl tdc tcdh figure 4. serial port write timing diagram cs sclk sdo high-z figure 5. serial port read timing diagram spol=0 tcdz tcdv
asahi kasei [AK61584] 0185-e-00 ?98/04 -9- switching characteristics - jtag (t a = -40 to 85 o c; tv+,rv+ = nominal +/- 0.3v; inputs: logic 0 = 0v, logic 1 =rv+) parameter symbol min typ max units cycle time t cyc 200 - - ns j_tms/j_tdi to j_tck rising setup time t su 50 - - ns j_clk rising to j_tms/j_tdi hold time t h 50 - - ns j_tclk falling to j_tdo valid t dv --50ns tcyc tsu th tdv j_tck j_tms j_tdi j_tdo figure 6. jtag swithing characteristics
asahi kasei [AK61584] 0185-e-00 ?98/04 -10- overview the AK61584 is a universal line interface for t1/e1 applications, designed for high-volume cards where low power, high density and universal op- eration is required. one board design can support all t1/e1 short-haul modes. the t1 and e1 modes can be selected entirely via software. as shown in figure 1, the AK61584 provides all the functions needed for a line interface including a line driver, a receiver and jitter attenuator. the line driver generates waveforms compatible with e1 (itu-t g.703),t1 short haul (dsx-1). the driver internally matches the impedance of the load, providing excellent return loss. the benefit of the internal impedance matching is a 50 percent reduction in power consumption compared to im- plementing return loss with external resistors. with external resistors a driver has to drive the equiva- lent of two line loads. the receiver contains clock and data recovery cir- cuits. the jitter attenuator meets at&t 62411 require- ments without the use of an external quartz crystal. the attenuator does require an external reference clock. vcc data rate refclk frequency mhz cable r1-r4 transformers volts mhz 1xclk=1 1xclk=0 ohm ohm t1-t4 1.544 1.544 12.352 100 12.5 1:2 3.3 2.048 2.048 16.384 75 21.5 1:1.32 120 34.4 figure 7 - typical connection diagram ( host mode) tclk1 tpos1 tneg1 rclk1 rpos1 rneg1 tclk2 tpos2 tneg2 rclk2 rpos2 rneg2 framer framer 0.47uf 0.47uf 470pf (e1) 470pf (e1) r1 r2 r3 r4 t1 1:n t2 1:n t3 1:n t4 1:n transmit receive transmit receive micro controller serial port control 12.352mhz clock refclk 1xclk clock ipol reset mode int cs sclk sdo sdi vcc control ttip1 tring1 rtip1 rring1 ttip2 tring2 rtip2 rring2 channel 1 channel 2 av+ agnd bgref tgnd2 tv+2 tv+1 power supply tgnd1 rgnd2 rv+2 rv+1 rgnd1 dv+ dgnd 1uf + 0.1uf vcc r3 5kohm 0.1uf 0.1uf 0.1uf 0.1uf + 3 22uf 0.01uf 0.47uf 0.47uf
asahi kasei [AK61584] 0185-e-00 ?98/04 -11- oper ating options the following are the major operating options which are supported by the AK61584: control control of the AK61584 is via either host mode (seri- al port) or hardware mode (individual control lines). hardware mode offers significantly fewer program- mability options than the host mode. t1/e1 the AK61584 supports t1 short-haul (dsx-1), and e1 operation. the configuration pins (con <0:2>) and register bits control transmitted pulse shapes, transmitter source impedance, and receiver slicing level. both channels must be operated at the same rate (both t1 or both e1). the pulse shapes are fully pre-defined by circuitry in the AK61584, and are fully compliant with appropri- ate standards when used with our application guideli- nes in standard installations. the transmitter impedance changes with the line length options in order to match the impedance of the load (75-ohm for e1 coax, 100-ohm for t1, 120- ohm for e1 shielded twisted pair). the receiver slicing level is set at 65% for dsx-1 short-haul, and at 50% for all other applications. line codes the AK61584 supports a transparent mode where the line code is encoded and decode by an external t1/e1 framing device. alternatively, a coder mode can be selected. in coder mode, an internal b8zs/ami/hdb3 coder can be used on those sys- tems which don't need t1/e1 framers (typically high -speed multiplexers). in host mode, the choice of transmit encoder is independent of the choice of re- ceiver decoder. reference clock the AK61584 requires a t1 or e1 reference clock. this clock can be either a 1-x clock (i.e. ,1.544 mhz or 2.048mhz). or can be a 8-x clock (i.e., 12.352 mhz or 16.384 mhz). in systems which want soft- ware selection of data rate, the 1 - x clock option is typically chosen, and the reference clock is tied to the transmit clock. in systems with a jittered transmit clock, an external oscillator should drive the reference clock input, and a 8-x rate can be used to minimize the physical size of the oscillator. in either case, any jitter present on the reference clock will not be filtered by the jitter attenuator, and the reference clock should have 100 ppm or better frequency accuracy. power down either one of the two line interfaces may be indepen- dently powered down. jitter attenuator the jitter attenuator may be placed in the receiver path, the transmit path or bypassed entirely.
asahi kasei [AK61584] 0185-e-00 ?98/04 -12- overview of applic ations this section summarizes a typical application of the AK61584 in various environments, and discusses what AK61584 options would normally be selected in that application. see figure 8. at&t 62411 customer premises application at&t 62411 applies at the t1 interface between the customer premises and the carrier, and must be implemented by the customer premises equipment. transmit transformer receive transformer ttip tring rtip rring line driver line receiver jitter attenuator AK61584 cs2180b framer circuit transmit transformer receive transformer ttip tring rtip rring line driver line receiver jitter attenuator AK61584 cs2180b framer circuit transmit transformer receive transformer ttip tring rtip rring AK61584 12.352mhz 32ppm 12.352mhz 100ppm refclk refclk refclk tpos tneg tclk rclk rpos rneg at&t 62411 application (systems with a single t1 line) mux tdata tclk (gapped) rclk rdata ami b8zs hdb3 coder jitter attenuator line driver ais detect line receiver asynchronous mux application (for example, vt1.5 card for sonet or sdh mux) synchronous application (including 62411 systems with multiple t1 lines) figure 8. configuration examples for various applicatons
asahi kasei [AK61584] 0185-e-00 ?98/04 -13- in 62411 applications, an overriding design considera- tion is management of jitter. typically, the AK61584 will use it's jitter attenuator on the receive side to re- duce the jitter seen by the system synchronizer. the transmit clock presented to the AK61584 by the system will be stratum 4 quality or better, and is input to both the reference clock pin and transmit clock pin. if an independent clock source is used for the reference clock, the jitter on the reference clock must be well below the jitter allowed by 62411. category i asynchronous multiplexer application asynchronous multiplexers take multiple t1/e1 lines (which are asynchronous to each other), and combine them into a higher speed transmission rate. examples are m13 muxes, and sonet muxes. in these systems, the jitter attenuator is used on the transmit side of the AK61584 to remove the waiting time jitter caused by the multiplexer. because the transmit clock is jittered, the reference clock to the AK61584 will be provided by an external quartz crystal, which operates at the 1-x or 8-x data rate. t1/e1 framers are typically not required in asynchronous multiplexers, so the b8zs/ ami/hdb3 coders in the AK61584 are activated. category ii synchronous application a typical example of a category ii application is a t1 card of a central office switch or a 0/1 digital cross-connect system. these systems use receive side jitter attenuation to reduce the jitter presented to the system, and will use a stratum 3 or better system clock to feed the AK61584 transmit and reference clocks. in these systems, a single hardware design can support t1 and/or e1 under software control since the rate of the transmit/reference clock rate will be varied by the sys- tem to match the line rate(t1 or e1). transmitter the transmitter takes data from a t1 or e1 terminal, and produces pulses of appropriate shape. the transmit clock (tclk) and transmit data (tpos & tneg, or tdata) are supplied synchronously. data is sampled on the falling edge of the input clock. pulse shaping and signal level are determined by con- figuration inputs as shown in table 1. typical output pulses are shown in figures 9 and 10. c c c o o o n n n 2 1 0 transmitter pulse width at pulse shape 50% amplitude receiver slicing level coder 0 0 0 0 0 1 244 ns(50%) e1:square, 2.37 volts into 75ohm 244 ns(50%) e1:square, 3.00 volts into 120ohm 50% 50% ami/hdb3 ami/hdb3 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 350 ns(54%) dsx-1:0-133ft 350 ns(54%) dsx-1:133-266ft 350 ns(54%) dsx-1:266-399ft 350 ns(54%) dsx-1:399-533ft 350 ns(54%) dsx-1:533-655ft 65% 65% 65% 65% 65% ami/b8zs ami/b8zs ami/b8zs ami/b8zs ami/b8zs con3 must be set to 0. table 1. configuration selection
asahi kasei [AK61584] 0185-e-00 ?98/04 14 -14- 269 ns (244 + 25) 194 ns (244 C 50) 244 ns 219 ns (244 C 25) 488 ns (244 + 244) 10% 10% 10% 10% 0% 50% 10% 10% 20% 20% v = 100% 20% nominal pulse note C v corresponds to the nominal peak value. figure 9. typical pulse shape at dsx-1 cross connect figure 10. mask of the pulse at 2048kbps interface the line driver internally matches the impedance of the line load, providing 14 db of return loss during the transmission of both marks and spaces. this improves signal quality by minimizing reflections off the trans- mitter. internal impedance matching reduces current consumption by factor of nearly two compared to return loss achieved by external resistors. the transmitter provides for all ones insertion at the frequency of refclk. transmit all ones is selected when taos goes high, and causes continuous ones to be transmitted on the line (ttip and tring). in this mode, the tpos and tneg, or tdata, inputs are ig- nored. when any transmit control pin (taos, lloop, or con<0 -2>) is toggled, the transmitter stabilizes within 22 bit periods. the transmitter will take longer to stabi- lize when rloop is selected because the timing cir- cuitry must adjust to the new frequency. recommended transmitter transformer specifica tions are shown below: when the transmitter transformer secondaries are shorted via a 0.5 ohm resistor, the transmitter will out- put a maximum of 50 ma-rms, as required by the bri- tish oftel otr-0001 specification. turns ratio 1:2 step-up for tx(t1) 1:2 step-down for rx(t1) 1:1.32 step-up for tx(e1) 1:1.32 step-down for rx(e1) primary inductance 1.5 mh min measured at 772 khz primary leakage inductance 0.3 uh max at 772 khz with secondary shorted secondary leakage inductance 0.4 uh max at 772 khz interwinding capacitance 18 pf max, primary to secondary et-constant 16 v-us min table 2(a). transformer requirements turns ratio part# manufacturer 1:2(t1) pe-65351 4023 pulse engineering jpc corporation 1:1.32(e1) 67148170 4022 schott corporation jpc corporation table 2(b) recommended transformer
asahi kasei [AK61584] 0185-e-00 ?98/04 -15- receiver the receiver extracts data and clock from the t1/e1 signal and outputs clock and synchronized data. the receiver can receive signals over the entire range of short haul cable lengths. the clock recovery circuit is a second-order phase lock loop, and can tolerate as much as 0.4u1 of jitter from 10 khz to 100khz, without error (figure 11). the clock and data recovery circuit is tolerant of long strings of consecutive zeros, and will successfully receive a 1-in-175, jitter- free input signal. figure 11. minimum input jitter tolerance of receiver (clock recovery circuit and jitter attenuator) data at rpos and rneg, is stable and may be sampled using the recovered clock. clke deter mines the clock polarity for which output data is stable and valid as shown in table 3. when clke is high, rpos and rneg are valid on the falling edge of rclk. when clke is low, rpos and rneg are valid on the rising edge of rclk. in hardware mode, the clke selec- tion is made via pin 27. in host mode, the clke selection is mode via control register (channel 1 control a, bit 7). clke data clock clock edge for valid data low rpos rneg rclk rclk rising rising high rpos rneg rclk rclk falling falling table 3. data output/data relationship the signal is detected differentially across the receive transformer. recommended receiver transformer specifications are identical to the transmit transformer specifications. receiver loss of signal the receiver will indicate loss of signal upon receiv- ing 175+/-15 consecutive zeros. a digital counter counts received zeros, based on recovered clock cy- cles. the receiver reports loss of signal by setting the appropriate loss of signal pin, los high. the los condition is exited using the ansi t1.231- 1993 criteria, namely 12.5% ones density for175+/-75 bit periods with no more than 100 zeros in a row. if a loss of signal condition occurs when the host mode is being used, the los and los-latched bits will be set and an interrupt will be issued. los will go low (and flag the interrupt pin again, if the serial i/o is used) when a valid signal is detected. the los-latched bit will stay high until read, and then will remain low until the next loss of signal event occurs. see figure 12. note that in the hosts mode serial port operation, los is simultane- ously available from both the register and pin losx. 1 10 100 300 700 1k 10k 100k jitter frequency(hz) 300 100 10 1 0.1 peak-to-peak jitter (unit intervals) 0.4 28 AK61584 performance at&t62411 (1990 version) los currently active (los bit & los pin) latched los (latch los bit) interrupt (int) read los bits "short" los event set by start of los set by change of los cleared by read cleared by read "long" los event figure 12 loss of signal event relationship
asahi kasei [AK61584] 0185-e-00 ?98/04 -16- when the jitter attenuator is in the receive path, upon loss of signal, the frequency of last re covered signal is held over. when the jitter attenuator is not in the re- ceive path, the last recovered frequency is not held over, rather, the output frequency will become the frequen- cy of the reference clock. any time a channel is reset or powered down, (for example by reset, pd1, pd2, or power-on reset), the loss of signal indicator on that channel is set high. the loss of signal indicator remains high until data is recovered by the receiver. receiver ais detection the receiver detects ais upon observation of 99.9% ones density for 5.3 ms. more specifically, the ais detection criteria is less than 9 zeros out of 8192 bits. when ais is detected, the AK61584 sets the control register bits ais and latched-ais, high. in the coder mode, the receiver also sets output pin ais high. the end of the ais condition occurs when > 9 zeros are detected out of 8192 bits. the ais bits in the status register operate the same as the los bits (see ta- ble5) upon detecting ais. when a channel is powered down, all indications are forced low. jitter attenu ator the jitter attenuator can be switched into either the receive or transmit paths. alternatively it can be removed from both paths (thereby decreasing propagation delay). atten0x atten1x location of jitter attenuator 0 0 receiver 0 1 transmitter 1 0 neither 1 1 reserved table 4. jitter attenuation control in hardware mode, the location of the attenuators is the same for channel 1 and 2, and is control led by pins atten0 and atten1. see table4. in host modes, figure 13. typical jitter transfer function the location of the attenuators is programmable on a per-channel basis, using bits atten01 and atten11 for channel 1, and bits atten02 and atten12 for channel 2. the control bits also conform to table 4. a typical jitter attenuation curve is shown in figure 13. the attenuator consists of a 64-bit fifo, a nar- row-band monolithic pll, and control logic. signal jitter is absorbed in the fifo. the fifo is designed to neither overflow nor underflow. if overflow or under- flow is imminent, the jitter transfer function is altered to insure that no bit errors occur. under this circumstance, jit- ter gain may occur, and jitter should be attenuated exter- nally in a frame buffer. the jitter attenuator will typi- cally tolerate 43 uis before the over flow/underflow mechanism takes effect. before the jitter attenuator has had time to lock to the average incoming frequency, for example, after a chip reset, the attenuator will tolerate a minimum of 22 uis before the overflow/underflow mechanism takes effect. for t1/e1 line cards employed in high-speed mul- tiplexers (e.g.,sonet and sdh), the jitter attenu- ator is typically used in the transmit path. the attenuator can be fed a gapped transmit clock, with gaps 22 uis, and transmit clock burst rate < 8 mhz.
asahi kasei [AK61584] 0185-e-00 ?98/04 -17- coder mode in the coder mode, three line codes are available: ami, b8zs and hdb3. the input to the encoder is tdata. the outputs from the decoder are rdata and bpv (bipolar violation strobe). in host modes, the encoder and decoder are selected using control register bits coder (1 = coder active, 0 = transparent mode, coder disabled) and ami-t/ami-r (1 =ami, 0 =b8zs or hdb3) where the transmitter and receiver can be inde- pendently controlled. the selection of b8zs versus hdb3 is made by the control bits: con<0:3>. in hardware mode, the encoder and decoder are controlled simultaneously by pins coder1 and coder2 (1 =coder active, 0 =transparent mode, coder disable). the line code is b8zs or hdb3. the selection of b8zs versus hdb3 is made by the pins: con<0:2>. in the coder mode, the receiver sets output pins ais1 and ais2 high, when ais is detected, respectively on channels 1 and 2. in the coder mode, pin bpv goes to a logic 1 for one bit period when a bipolar violation is detected in the received signal. b8zs (or hdb3) zero substitutions are not flagged as bipolar violations if the b8zs (or hdb3) decoder has been enabled. a latched-bpv indica- tion is also available in the status register. reference clock the AK61584 requires a t1 or e1 reference clock. this clock is input on pin refclk, and can be either a 1-x clock (i.e. ,1.544 mhz or 2.048 mhz), or a 8-x clock (i.e.,12.352 mhz or 16.384 mhz). pin 1xclk determines which option is used (active high for 1-x, and low for 8-x). any jitter present on the reference clock will not be filtered by the jitter attenuator, and will be present on the output of the jitter attenuator. the reference clock should have a minimum accuracy of 100 ppm. loopbacks local loopbacks the two local loopbacks take clock and data pre sented on tclk, tpos, and tneg, or tdata and out- puts it at rclk, rpos and rneg, or rdata. as shown in the block diagram on the first page of the data sheet, loopback 1 includes the jitter attenuator. loop- back 2 includes the line driver and the receiver. for both local loopbacks, i nputs to the transmitter are still transmitted on the line, unless taos has been se- lected in which case, ami-coded continuous ones are transmitted to the line at the rate determined by tclk. receiver inputs are ignored when local loopback is in effect. local loopback 1 is selected by a control pin, or a control bit. loopback 2 is selected only via a con- trol bit. remote loopback in remote loopback, the recovered clock and data input on rtip and rring are sent back out on the line via ttip and tring as shown in the block diagram on the front page of this data sheet. the recovered in- coming signals are also sent to rclk, rpos and rneg, or rdata. a remote loopback may be selected in both the hardware and host modes. simultaneous selec- tion of local and remote loopback modes is not valid. power down the pd1 and pd2 pins reset, respectively, the trans- mitter, receiver and jitter attenuator of channels 1 and 2. whenever pd1 or pd2 is selected, the selected channel remains powered down, and the outputs (pins rclk, rpos, rneg, rdata, bpv, ais, ttip, and tring) associated with that channel are put into a high-impedance state, and pin los is set high. addi- tionally, the status register bits are reset. the control, mask, and arbitrary waveform registers are unchanged.
asahi kasei [AK61584] 0185-e-00 ?98/04 -18- the non-selected channel operates normally. selecting pd1 or pd2 does not reset the AK61584 control reg- isters, or serial control ports. simultaneously selecting pd1 and pd2 will power down some additional analog circuitry that is shared by both channels. after exiting the power down state, the channel will be fully operational in less than 20 ms. reset in operation, the AK61584 is continuously cali brated, making the performance of the device independent of power supply or temperature variations. the continuous calibration function forgoes any requirement to reset the line interface when in operation. the reset pin resets the entire device, includ ing the control logic, and clears all control and mask registers. a reset event results in the latched-reset bit being set in the status register. a reset request can be made by setting reset high for at least 200 ns. reset will ini- tiate on the falling edge of reset. the reset operation takes less than 20 ms to complete. upon exiting reset, both channels are powered up. power on reset upon power-up, the ic is held in a static state until the supply crosses a threshold of approximately 60% of the power supply voltage. when this threshold is crossed, the device will delay for about 10 ms to allow the power supply to reach operating voltage. after this delay, cali- bration of the transmit and receive sections commences. the calibration can take place only if refclk and tclk are present. the initial calibration takes less than 20 ms. the power-on reset has the same effect as the reset. a power-on reset event results in the latched-reset bit being set in the status register. control control of the AK61584 is via either host mode (regis- ter read/write via serial control port), or hardware mode (individual control pin). hardware mode offers significantly fewer programmability options than the host mode. the following pins are used to select the mode. the mode pin active low selects hardware mode. the mode pin active high enables host mode. once host mode is invoked, the pin 16 must be set to logic low. the definition of the pins in each mode is shown in the block diagram of the first page of the data sheet. hardware mode the following control options are available in hard- ware mode on a per channel basis: power down, remote loopback, transmit all ones, coder mode, line length selection and location of jitter attenuator. host modes host mode allows a microcontroller to read/write ten AK61584 control and status registers. the registers are defined in table 5, and discussed in a later section. host mode interface ports are available for serial. in host mode, the AK61584 registers occupies a six-bit address space, where those six bits select a register in the range h10 to h19. the AK61584 generates an interrupt on pin int whenever a status register changes. the polarity of the int pin is programmable. when the ipol pin is high, int goes high to generate a proces sor interrupt. when the ipol pin is low, int goes low to generate a processor interrupt.
asahi kasei [AK61584] 0185-e-00 ?98/04 -19- registers the control and status registers are defined in table 5, and are accessible in host mode. each channel has its own set of status, mask and control. the status register is read -only. writing to the status register has no impact on its contents. interrupts are generated on the int pin every time a status register changes. reading a status register resets all bits in that status register to 0. the mask reg- ister allows the user to mask interrupts on a status register on a per-bit basis. the control registers select fea- tures /functionality. status registers description each bit in the status register is defined below. ais and latched-ais: indicates an all-ones condition. ais is set high while ais condition is currently de- tected. latched-ais indicates that a ais condition has occurred since the last read of the status register. interrupt: indicates that the status register has changed sometime since the last read of the status register. l atched-bpv: indicates a bipolar violation event has been detected in the receiver sometime since the last read of the status register. this bit is set only when the line -code decoder is enabled. latched-overflow: indicates that a waveform generated using the arbitrary waveforms has exceeded full scale sometime since the last read of the status reg ister. (optional information, refer to the application note.) los and latched-los : indicates loss of signal condition. los is set high while los condition is currently detected. latched-los indicates that a los condition has occurred since the last read of the status register. latched-reset: indicates that a reset event (power-up or manual) has occurred since the last read of the status register. this status bit is not maskable. definition reset register address bit name 1 0 value h10 b0000 channel 1 status 7 6 5 4 3 2 1 0 los1 latched-los1 ais1 latched-ais1 latched-bpv1 latched -overflow1 latched-reset interrupt1 los currently detected los event since last read ais currently detected ais event since last read bpv event since last read pulse overflow since last read reset event since last read interrupt event since last read no los no los no ais no ais no bpv no overflow no reset no interrupt 1 1 0 0 0 0 1 0 h11 b0001 channel 2 status 7 6 5 4 3 2 1 0 los2 latched-los2 ais2 latched-ais2 latched-bpv2 latched -overflow2 reserved interrupt2 los currently detected los event since last read ais currently detected ais event since last read bpv event since last read pulse overflow since last read interrupt event since last read no los no los no ais no ais no bpv no overflow no interrupt 1 1 0 0 0 0 0 0 table 5(a). status registers
asahi kasei [AK61584] 0185-e-00 ?98/04 -20- definition reset register address bit name 1 0 value h10 b0010 channel 1 mask 7 6 5 4 3 2 1 0 mask los1 mask latched- los1 mask ais1 mask latched- ais1 mask latched- bpv1 mask latched -overflow1 reserved mask interrupt1 mask status bit 7 mask status bit 6 mask status bit 5 mask status bit 4 mask status bit 3 mask status bit 2 mask status bit 0 & interrupt pin enable status bit 7 enable status bit 6 enable status bit 5 enable status bit 4 enable status bit 3 enable status bit 2 enable status bit 0 & interrupt pin 0 0 0 0 0 0 0 0 h11 b0011 channel 2 mask 7 6 5 4 3 2 1 0 mask los2 mask latched- los2 mask ais2 mask latched- ais2 mask latched- bpv2 mask latched -overflow2 reserved mask interrupt2 mask status bit 7 mask status bit 6 mask status bit 5 mask status bit 4 mask status bit 3 mask status bit 2 mask status bit 0 & interrupt pin enable status bit 7 enable status bit 6 enable status bit 5 enable status bit 4 enable status bit 3 enable status bit 2 enable status bit 0 & interrupt pin 0 0 0 0 0 0 0 0 note)mask los and mask latched-los need to controlled simultaneously, and mask ais and mask latched-ais also. table 5(b). mask registers mask registers description writing a 1 to a bit of the mask register forces the corre- sponding bit of the status register to stay fixed at 0. control a registers description each bit in the control register is defined below. ami-r: writing a 0enables the b8zs or hdb3 decoder in the receiver path. b8zs vs. hdb3 se- lection is determined by the con<0:2> bits. writing a 1 enables the ami decoder. ami-t: writing a 0 enables the b8zs or hdb3 encoder in the transmit path. b8zs vs. hdb3 se- lection is determined by the con<0:2> bits. writing a 1 enables the ami encoder. clke: when clke is set to 1. rpos and rneg are valid on the falling edge of rclk. when clke is set to 0, rpos and rneg are valid on the rising edge of rclk. this bit con- trols the rpos/rneg polarity for both host modes. the clke pin provides the same function- ality for the hardware mode.
asahi kasei [AK61584] 0185-e-00 ?98/04 -21- definition reset register address bit name 1 0 value h14 b0100 channel 1 control a 7 6 clke pd1 rpos/rneg valid on falling rclk power down channel 1 rpos/rneg valid on rising rclk power up channel 1 0 0 5 atten01 atten01 attenn11 0 4 atten11 0 0 1 0 1 0 attenuator 1 in receiver path attenuator 1 in transmit path attenuator 1 inactive 0 3 2 1 0 coder1 ami-t1 ami-r1 factory test 1 coder/mode enabled ami encoder enabled ami decoder enabled test transparent mode enabled b8zs/hdb3 encoder enabled b8zs/hdb3 decoder enabled normal operation 0 0 0 0 h15 b0101 channel 2 control a 7 6 reserved pd2 must be set to 0 power down channel 2 power up channel 2 0 0 5 atten02 atten02 atten12 0 4 atten12 0 0 1 0 1 0 attenuator 2 in receiver path attenuator 2 in transmit path attenuator 2 inactive 0 3 2 1 0 coder2 ami-t2 ami-r2 factory test coder/mode enabled ami encoder enabled ami decoder enabled test transparent mode enabled b8zs/hdb3 encoder enabled b8zs/hdb3 decoder enabled normal operation 0 0 0 0 table 5(c). control a registers coder: writing a 1 enables a coder (ami, b8zs or hdb3), and enables pins tdata, rdata, ais and bpv. writing a 0 disables the coder, plac- ing the channel in transparent mode, and enables pins tpos, tneg, rpos and rneg. factory test: must be set to 0 for normal operation. pd: writing a 1 powers down the channel. control b registers description each bit in the control register is defined below. con<0:2>: controls the configuration of the trans- mitter, receiver and coder as shown in table 1. both channels must operate at the same rate ( both t1 or both e1). specifications are not guaranteed with the channels operating at differ ent rates. after a manual or power-on reset, the con bits are reset to the e1 rate. if a single channel t1 mode is desired (i.e., second channel is not used), it is recommended that both chan- nels be set to the t1 rate. lloop1: writing a 1 enables local loopback #1, as shown in the block diagram on the front page of the data sheet. lloop2: writing a 1 enables local loopback #2, as shown in the block diagram on the front page of the data sheet. rloop: writing a 1 enables remote loopback for this channel. taos: writing a 1 enables transmit all ones.
asahi kasei [AK61584] 0185-e-00 ?98/04 -22- definition reset register address bit name 1 0 value h16 b0110 channel 1 control b 7 6 5 4 3 2 1 0 taos1 rloop1 lloop11 lloop21 con31 con21 con11 con01 enable transmit all ones enable remote loopback enable local loopback #1 enable local loopback #2 must be set to 0 see table 1 see table 1 see table 1 disable transmit all ones disable remote loopback disable loopback #1 disable loopback #2 0 0 0 0 0 0 0 0 h17 b0111 channel 2 control b 7 6 5 4 3 2 1 0 taos2 rloop2 lloop12 lloop22 con32 con22 con12 con02 enable transmit all ones enable remote loopback enable local loopback #1 enable local loopback #2 must be set to 0 see table 1 see table 1 see table 1 disable transmit all ones disable remote loopback disable loopback #1 disable loopback #2 0 0 0 0 0 0 0 0 table 5(d). control b registers note) con3 is used for arbitrary waveform generation. please connect to 0 for the normal operation. register address bit name definition reset value h18 b1000 channel 1 arbitrary pulse shape 7 6 5 4 3 2 1 0 msb lsb undefined undefined undefined undefined undefined undefined undefined undefined h19 b1001 channel 2 arbitrary pulse shape 7 6 5 4 3 2 1 0 msb lsb undefined undefined undefined undefined undefined undefined undefined undefined table 5(e). arbitrary waveform registers
asahi kasei [AK61584] 0185-e-00 ?98/04 -23- host mode register access this mode is selected by setting pin mode to logic high, and pin 16 must be set to logic low. in the host mode, the on-board registers can be written to via the sdi pin or read from via the sdo pin at the clock rate determined by sclk. through these registers, a host controller can be used to control operational char- acteristics and monitor device status. the serial port read/write timing is independent of the system transmit and receive timing. any read or write to the serial port is initiated by setting chip select (cs) low and writing an 8 -bit ad- dress/command byte (acb). the acb consists of the three separate fields including a 6 -bit register address (see figure 14). the acb is followed by a data word. in the acb, d0(lsb) is the r/w field, and specifies whether the current operation is to be a read or a write: 1 = read, 0= write. the next 4 bits (d1-d4) contain the address field. they specify which of the registers to access. d5 and d6 are dont care bits. setting bit d7 to 1 selects burst mode (described below). registers h10 to h17 are read and written as described above. registers h18 and h19 are used to access mul- tiple bytes for the arbitrary waveform generation, refer to the AK61584 application note. another communication option, burst mode, is available. burst mode is specified by setting bit d7(msb) of the acb to 1. burst mode allows multiple registers to be consecutively read or written. writing all registers allows fast initi alization at power-up or system reset. when using burst mode, the address field of the acb command word must be h00. the registers are read or written in address order h10 to h11, followed by 42 byte reads or writes to register h18, followed by 42 bytes read or writes to register h19. burst mode ends on the first rising edge of cs, and may be ended at any time. if a burst write ends before writing 92 bytes, the remaining, unwritten bytes are unchanged. figure 15 shows the timing relationships for data transfers. when the spol pin is high, data on sdo is valid on the falling edge of sclk. when the spol pin is low, data on sdo is valid on the rising edge of sclk. all data is written to and read from the port lsb first. when writing to the port, sdi input data is sam- pled on the rising edge of sclk. sdo goes to high impedance state when not in use. sdo and sdi may be tied together in applications where the host processor has a bi-directional i/o port. cs sclk sdi sdo r/w 0 0 00 00 1 address/command byte data input/output d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 figure 15. serial read/write timing 7 bm 6 5 43 21 0 0 1 0 1 add5 add3 add4 add2 add1 add0 r/w individual burst (msb) register address field (lsb) write read (msb) (lsb) figure 14. address command byte (acb) don't care
asahi kasei [AK61584] 0185-e-00 ?98/04 -24- arbitrary waveform registers these registers are written multiple times to enter an arbitrary waveform. arbitrary wa veform gener ation in additon to the predefined pulse shapes, the user can create arbitrary pulse shapes using the host mode for evaluation. refer to the AK61584 application note. power supply the device operates from a single 3.3 volt supply. separate pins for the various supplies provide internal isolation. however, these pins should be connected ex- ternally with the power supply pins de-coupled to their respective grounds. the various ground pins must not be more negative than agnd. de-coupling and filtering of the power supplies is cru- cial for the proper operation of the analog circuits. the best way to configure the power supplies is to tie all of the supply pins together at the chip. as shown in figure 1, a capacitor should be connected between each supply and its respective ground. for the 1uf and smaller cap acitors, use mylar or ceramic capacitors and place them as closely as possible to their respective power supply pins. wire-wrap bread boarding of the line interface is not recommended because lead resistance and inductance serve to defeat the func- tion of the de-coupling capacitors. a 5kohm, 1%, resistor should connect bgref to ground. jtag boundary scan jtag boundary scan supports board testing. using boundary scan, the integrity of the digital paths between ics on a board can be verified. this verification is supported by the ability to externally set the signals on the AK61584's digital output pins, and to externally read the signals present on the AK61584's input pins. as shown in figure 16, the jtag hardware consists of data and instruction registers plus a test access port ( tap) controller. control of the tap is achieved through signals applied to the test mode select (j_tms) and test clock (j_tck) input pins. data is shifted into the registers via the test data input (j_tdi) pin, and shifted out of the registers via the test data output (j_tdo) pin, again using j_tck. the instruction register defines which data register is included in the shift operation. note that if j_tdi is left floating, an internal pull-up resistor forces the pin high. jtag data registers (dr) the test data registers are: the boundary-scan regiser (bsr), and the bypass register (br). boundar y scan data re g ister 32bit data re g ister ( factor y use onl y ) b y pass data re g ister instruction ( shift ) re g ister parallel latched output parallel latched output parallel latched output tap controller mux di g ital output pins di g ital input pins j-tdi j-tck j-tms j-tdo jtag block figure 16. jtag circuitry block diagram
asahi kasei [AK61584] 0185-e-00 ?98/04 -25- boundary scan register: the bsr can be connected in parallel to all the digital i-o pins, and provides the mechanism for applying/reading test patterns to/from the board traces. the bsr is initialized and read using the instruction sample/preload. the bit ordering for the bsr is the same as the top-view packaged pin out, counter -clockwise beginning with pd1 (pin 15) and ending with los1 (pin 7), as shown in table 6. the analog, oscillator, power, ground, atten0, clke and mode pins are not included as part of the boundary- scan register. atten0, clke and mode are not included because they are typically hard-wired to power or ground on a board. all output pins are 3-state pins (logic high, logic low or high impedance); their value can be set via the preload/extest instructions. since outputs are all 3-state, 2 bits are required to specify the states of each output pin in the bsr. the first bit (which is shifted in first) contains the testing data which may be output on the pin. the second bit, which is shifted in following the first bit, selects between an output-enabled state (bit set to 1) or high-impedance state (bit set to 0). thus, two j_tck cycles are required to load testing data for each output pin. each input pin requires only 1 bit in the bsr. the bi-directional pins, tneg1/ais1, tneg2/ais2, int/rloop1, los1, los2, lloop1/sclk, lloop2/sdo, taos1/sdi, taos2/spol, and the con<0:2> pins have three bits in the bsr. the first bit shifted into the bsr captures the value of the pin. this pin may have its value set externally (if the third bit is 0) or set internally (if the third bit is 1). the second bit shifted into the bsr sets the output value. this value is output on the pin when the third bit is 1. the third bit con- figures the output driver as high-impedance (bit set to 0) or active (bit set to 1). note that the interrupt pin on the AK61584 has the ability of being a active high or active low signal. in host mode, the ipol pin controls this functionality. during jtag testing in host mode, the polarity of the int pin will be determined by the state of the ipol pin. the int pin on the AK61584 should not be configured as an output by the jtag bsr if the device is in hard- ware mode. likewise, the int pin should not be config- ured as an input by the jtag bsr if the device is in host mode. thus, the entire bsr is 62 bits long. bsr bits pin name pin # pad type 1 pd1 15 input 2 ipol,rloop2 33 input 3 pd2 34 input 4 coder2 41 input 5-7 los2 42 bi-directional 8-10 tneg2,ais2 43 bi-directional 11 tpos2,tdata2 44 input 12 tclk2 45 input 13-14 rneg2,bpv2 46 output 15-16 rpos2,rdata2 47 output 17-18 rclk2 48 output 19 coder1 49 input 20 con22 50 input 21-23 con21 51 bi-directional 24-26 con12 52 bi-directional 27-29 con11 53 bi-directional 30-32 con02 54 bi-directional 33-35 con01 58 bi-directional 36-38 taos2 59 bi-directional 39-41 sdi, taos1 60 bi-directional 42-44 sdo,lloop1 61 bi-directional 45 sclk,lloop2 62 input 46-48 int,rloop1 63 bi-directional 49 cs,atten1 64 input 50-51 rclk1 1 output 52-53 rpos1,rdata1 2 output 54-55 rneg1,bpv1 3 output 56 tclk1 4 input 57 tpos1,tdata1 5 input 58-60 tneg1,ais1 6 bi-directional 61-63 los1 7 bi-directional table 6 boundary scan register contents bypass register: the bypass register consists of a single bit, and provides a serial path between j_tdi and j_tdo, bypassing the bsr. the provision of this register allows the bypassing of those segments of the board-level serial test register which are not required for a specific test. this also reduces test access times, by reducing the total num- ber of shifts required from j_tdi to j_tdo.
asahi kasei [AK61584] 0185-e-00 ?98/04 -26- jtag instructions and instruction register (ir) the instruction register (2 bits) allows the in struction to be shifted into the circuit. the instruction is used to select the test to be performed or the data register to be accessed or both. the valid instructions are (lsb shifted in first): ir code instruction 00 extest 01 sample/preload 11 bypass extest instruction: the extest instruction allows testing of off-chip circuitry and board-level interconnect. extest connects the bsr to j_tdi and j_tdo. the normal path between the AK61584 logic and it's io pins is broken; the sig- nals on the output pins are loaded from the bsr; the signals on the input pins are loaded into the bsr. sample/preload instruction: the sample/pre-load instructions allows scanning of the boundary-scan register without interfering with the operation of the AK61584. this instruction connects the bsr to j_tdi and j_tdo. the normal path be- tween the AK61584 logic and its io pins is main- tained; the signals on those io pins is maintained; the signals on those 10 pins are loaded into the bsr. addi- tionally, this instruction can be used to latch values into the digital output pins. bypass instruction: the bypass instruction connects the minimum length, bypass register between j_tdi and j_tdo, and allows data to be shifted in the shift-dr controller state. internal testing considerations note that the intest instruction is not supported be- cause of the difficulty of performing signifi cant internal tests using jtag. the most complete internal test would involve inputting digital data on pins tclk, tpos, tneg, activating local loopback#2, and reading that same data out on pins rclk, rpos and rneg. this test would include the full transmit path, the full receive path, and optionally, the jitter attenuator, and provides excellent test coverage of the functional blocks. however, this test is diffi- cult to implement for two reasons. first, tclk and refclk must be clocked at specific frequencies, e.g., t1/e1+/-200 ppm for tclk. if these frequency requirements are not met, the per- formance of the transmitter, clock recovery circuit and jitter attenuator is not guaranteed. if would be difficult with jtag to toggle the tclk input at the required rate. second, the loopback path includes two asynchro nous blocks, clock recovery and jitter attenuator. therefore, the exact time delay for a tpos-input appearing on rpos -output is variable, making output signature correlation difficult. the one test that could be easily performed using an ar- bitrary clock rate on tclk and refclk is local loopback#1, with jitter attenuator disabled. however, that test provides such limited fault coverage, that is only useful in determining if the device had been catastrophically destroyed. alternatively, catastrophic destrucion of the ic and/or surrounding board traces can be detected using extest. therefore, the in- test instruction was viewed as providing little significant incremental testing capability, while ad- ding to product complexity, and was not included in the AK61584. jtag tap controller figure 20 shows the state diagram for the tap state machine. a description of each state follows. note that the figure contains two main branches to access either the data or instruc tion registers. the value shown next to each state transition in this figure is the value present at j_tms at each rising edge of j_tck.
asahi kasei [AK61584] 0185-e-00 ?98/04 -27- test-logic-reset state in this state, the test logic is disabled so that normal opera- tion of the device can continue unhindered. during initialization, the AK61584 initializes the instruction register. no matter what the original state of the controller, the controller enters test-logic-reset state when the j_tms input is held high (logic 1) for at least five rising edges of j_tck. the controller remains in this state while j_tms is high. the AK61584 proces- sor automatically enters this state at power-up. run- test/idle state this is a controller state between scan opera tions. once in this state, the controller remains in this state as long as j_tms is held low. the instruction register and all test data registers retain their previous state. when j_tms is high and a rising edge is applied to j_tck, the controller moves to the select-dr state. select-dr-scan state this is a temporary controller state. the test data register selected by the current instruction retains its previous state. if j_tms is held low and a rising edge is applied to j_tck when in this state, the controller moves into the capture -dr state, and a scan sequence for the selected test data register is initiated. if j_tms is held high and a rising edge applied to j_tck, the controller moves to the select-ir-scan state. the instruction does not change in this state. capture-dr state in this state, the boundary scan register cap tures input pin data if the current instruction is extest or sample/preroad. the other test data registers, which to not have parallel input, are not changed. the instruction does not change in this state. when the tap controller is in this state and a rising edge is applied to j_tck, the controller enters the exit1-dr state if j_tms is high or the shift-dr state if j_tms is low. figure 17. tap controller state diagram select-dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr test-logic-reset run- test/idle select-ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 0 1 0 1 1 0 1 1 0 0 0 1 0 0 1 0 1 1 0 1 0 0 1 1 0 0 0 1 1 1 1
asahi kasei [AK61584] 0185-e-00 ?98/04 -28- shift-dr state in this controller state, the test data register connected between j_tdi and j_tdo as a result of the current in- struction shifts data on stage toward its serial output on each rising edge of j_tck. the instruction does not change in this state. when the tap controller is in this state and a rising edge is applied to j_tck, the controller enters the exit1-dr state if j_tms is high or remains in the shift-dr state if j_tms is low. exit1-dr state this is a temporary state. while in this state, if j_tms is held high, a rising edge applied to j_tck causes the controller to enter the update-dr state, which termi- nates the scanning process. if j_tms is held low and a rising edge is ap plied to j_tck, the controller enters the pause-dr state. the test data register selected by the current in struction re- tains its previous value during this state. this instruction does not change in this state. pause-dr state the pause state allows the test controller to tem porarily halt the shifting of data through the test data register in the serial path between j_tdi and j_tdo. an example use of this state could be to allow tester to reload its pin memory from disk during application of a long test sequence. the test data register selected by the current instruc- tion retains its previous value during this state. the instruction does not change in this state. the controller remains in this state as long as j_tms is low. when j_tms goes high and a rising edge is applied to j_tck, the controller moves to the exit2-dr state. exit2-dr state this is a temporary state. while in this state, if j_tms is held high, a rising edge applied to j_tck causes the controller to enter the update-dr state, which terminates the scanning process. if j_tms is held low and a rising edge is applied to j_tck, the controller enters the shift -dr state. the test data register selected by the current instruc- tion retains its previous value during this state. the instruction does not change in this state. updata-dr state the boundary scan register is provided with a latched parallel output to prevent changes at the parallel output while data is shifted in response to the extest and sample/preload instructions. when the tap controller is in this state and the boundary scan register is selected, data is latched onto the parallel output of this register from the shift-register path on the falling edge of j_tck. the data held at the latched parallel output does not change other than in this state. all shift -register stages in the test data register selected by the current instruction retains their previous value during this state. the instructions does not change in this state. select-ir-scan state this is a temporary controller state. the test data register selected by the current instruction retains its previous state. if j_tms is held low and a rising edge is applied to j_tck when in this state, the controller moves into the capture-ir state, and a scan sequence for the instruction register is initiated. if j_tms is held high and a rising edge is applied to j_tck, the controller moves to the test-logic -reset state. the instruction does not change in this state.
asahi kasei [AK61584] 0185-e-00 ?98/04 -29- capture-ir state in this controller state, the shift register co ntained in the instruction register loads a fixed value of 01 on the ris- ing edge of j_tck. this supports fault-isolation of the board-level serial test data path. data registers selected by the current instruction retain their value during this state. the in struction does not change in this state. when the controller is in this state and a rising edge is ap- plied to j_tck, the controller enters the exit1-ir state if j_tms is held high, or the shift-ir state if j_tms is held low. shift-ir state in this state the shift register contained in the instruction register is connected between j_tdi and j_tdo and shifts data one stage towards its serial output on each rising edge of j_tck. the test data register selected by the current instruc- tion retains its previous value during this state. the instruction does not change in this state. when the controller is in this state and a rising edge is ap- plied to j_tck, the controller enters the exit1-ir state if j_tms is held high, or re- mains in the shift-ir state if j_tms is held low. exit1-ir state this is a temporary state. while in this state, if j_tms is held high, a rising edge applied to j_tck causes the controller to enter the update-ir state, which termi- nates the scanning process. if j_tms is held low and a rising edge is applied to j_tck, the controller enters the pause -ir state. the test data register selected by the current instruc- tion retains its previous value during this state. the instruction does not change in this state. pause-ir state the pause state allow the test controller to tempo- rarily halt the shifting of data through the instruction register. the test data register selected by the current instruc- tion retains its previous value during this state. the in- struction does not change in this state. the controller remains in this state as long as j_tms is low. when j_tms goes high and a rising edge is ap- plied to j_tck, the controller moves to the exit2-ir state. exit2-ir state this is a temporary state. while in this state, if j_tms is held high, a rising edge applied to j_tck causes the controller to enter the update-ir state, which termi- nates the scanning process. if j_tms is held low and a rising edge is applied to j_tck, the controller enters the shift -ir state. the test data register selected by the current instruc- tion retains its previous value during this state. the instruction does not change in this state. updata-ir state the instruction shifted into the instruction register is latched onto the parallel output from the shift-register path on the falling edge of j_tck. once the new instruction has been latched, it becomes the cur- rent instruction. test data registers selected by the current instruction retain their previous value. jtag application examples figures 18 and 19 show examples of updating the in- struction register and data registers.
asahi kasei [AK61584] 0185-e-00 ?98/04 -30- figure 18.test logic operation: instruction scan
asahi kasei [AK61584] 0185-e-00 ?98/04 -31- figure 19. test logic operation: data scan
asahi kasei [AK61584] 0185-e-00 ?98/04 -32- dgnd1 con01 taos2 taos1 lloop2 lloop1 rloop1 atten1 rclk1 rpos1(rdata1) rneg1(bpv1) tclk1 tpos1(tdata1) tneg1(ais1) los1 j-tdo dgnd2 j-tdi ttip1 tv+1 tgnd1 tring1 pd1 atten0 rtip1 rring1 rv+1 rgnd1 mode bgref agnd av+ dv+ dgnd3 con02 con11 con12 con21 con22 coder1 rclk2 rpos2(rdata2) rneg2(bpv2) tclk2 tpos2(tdata2) tneg2(ais2) los2 coder2 j-tck j-tms ttip2 tv+2 tgnd2 tring2 pd2 rloop2 rtip2 rring2 rv+2 rgnd2 1xclk clke refclk reset pin description 1 a k61584 64 - pin l q fp hardware mode top view 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
asahi kasei [AK61584] 0185-e-00 ?98/04 -33- dgnd1 not used * spol sdi sdo sclk int cs rclk1 rpos1(rdata1) rneg1(bpv1) tclk1 tpos1(tdata1) tneg1(ais1) los1 j-tdo dgnd2 j-tdi ttip1 tv+1 tgnd1 tring1 pd1 must be set to 0 rtip1 rring1 rv+1 rgnd1 mode bgref agnd av+ dv+ dgnd3 not used* not used* not used* not used* not used* not used* rclk2 rpos2(rdata2) rneg2(bpv2) tclk2 tpos2(tdata2) tneg2(ais2) los2 not used* j-tck j-tms ttip2 tv+2 tgnd2 tring2 pd2 ipol rtip2 rring2 rv+2 rgnd2 1xclk not used# refclk reset pin description 1 a k61584 64- pin lqfp host mode - serial port top view note:*not used pins are recommended to be tied to dgnd #not used pins are recommended to be tied to agnd 5 6 5 5 5 4 5 3 5 2 51 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 41 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 31 3 0 2 9 2 8 2 7 2 6 2 5 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 2 0 2 1 2 2 2 3 2 4 pin 16 must be set to logic 0
asahi kasei [AK61584] 0185-e-00 ?98/04 -34- power supplies agnd-ground, analog, pin 23. analog supply ground pin. av+ -power supply, analog, pin 24 analog supply ground pin for internal bandgap reference, oscillator and internal clock multipliers bgref-bandgap reference, pin 22 used by the internal bandgap reference. this pin should be connected to ground by a 5k ohm resister dgnd1, dgnd2, dgnd3 -ground, pins 57, 9, 55. power supply ground pin for the digital circuitry in both channels. dv+ -power supply, pin 56 power supply pin for the digital circuitry in both channels.; typically +3.3 volts referenced to dgnd. rgnd1, rgnd2 -ground, receiver, pins 20, 29. power supply ground pins for the receivers. rv+1, rv+2 -power supply, receiver, pins 19, 30. power supply pins for the analog circuitry in the receivers; typically +3.3 volts referenced to rgnd1 and rgnd2. tgnd1, tgnd2 -ground, transmit drivers, pin 13, 36 power supply ground pins for the transmitters. tv+1, tv+2 -power supply, transmit drivers, pins 12, 37. power supply pins for the transmitter analog circuitry; typically +3.3 volts references to tgnd1 and tgnd2. control pins and control buses atten0 atten1 -jitter attenuator select, pin 16, 64. (hardware mode) selects, for both channels, which path has jitter attenuation (transmit/receive/neither). see table 4. in host mode, pin 16 must be tied to gnd. clke -clock edge, pin 27. (hardware mode) clke controls rclk polarity. setting clke to logic 1 causes rpos and rneg (rdata) to be valid on the falling edge of rclk. conversely, setting clke to logic 0 causes rpos and rneg (rdata) to be valid on the rising edge of rclk. coder1,coder2-coder enable, pins 49, 41. (hardware mode) setting coder to logic 1 enables a coder (b8zs or hdb3),setting coder to logic 0 transparent mode enables.
asahi kasei [AK61584] 0185-e-00 ?98/04 -35- con01, con11, con21, con02. con12, con22 -configuration selection, pins 58, 53, 51, 54, 52, 50. (hardware mode) configures the transmitter (pulse shape, pulse width, pulse amplitude and driver impedance), receiver (slicing level), and coder (hdb3 vs b8zs)as shown in table 1. the conx1 pins control channel 1. the conx2 pins control channel 2. both channels must operate at the same rate (both t1 or both e1). cs -chip select, pin 64. (host modes) pin most transition from high to low to read or write the serial port. int -receive alarm interrupt, pin 63. (host mode) an interrupt is generated when a status register changes state to flag the host processor. int is cleared by reading the status registers. the logic level for an active interrupt alarm is controlled by pin ipol. int is an open drain output and should be tied to the appropriate supply through a resistor. ipol -interrupt polarity, pin 33. (host mode) ipol controls int polarity. setting ipol to logic 1 causes interrupts to be indicated by int equal high. setting ipol to logic 0 causes interrupts to be indicated by int equal to low. lloop1, lloop2 -local loopback, pin 62,61. (hardware mode) setting lloop to a logic 1 activates local loopback #1. tclk and tpos/tneg (tdata) are still transmitted unless overridden by a taos request. inputs on rtip and rring are ignored. mode -mode select, pin 21. setting mode to logic 1 puts the line interface in the host mode. in the host mode, a serial interface is used to control the line interface and monitor its status. setting mode to logic 0 puts the line interface in the hardware mode, where it is configured and monitored using discrete pins. mode defined the function of pins shown across the top of the block diagram on the front page of the data sheet. setting mode to av+/2 volts will cause unpredictable results. pd1, pd2 - power down, pins 15, 34. setting pd1 or pd2 to logic 1 puts the channel 1 or channel 2 line interface, respectively, in a low power, inactive state. setting pd1 or pd2 to logic 0 returns the selected channel to normal operation. reset -reset, pin 25. setting reset to logic 1 resets the AK61584, clears the host-mode control registers, and then sets los high. rloop1,rloop2-remote loopback, pins 63,33. (hardware mode) setting rloop to a logic 1 causes the recovered clock and data on both channels to be sent through the driver back to the line. the recovered signal is also sent to rclk and rpos/rneg .(rdata)
asahi kasei [AK61584] 0185-e-00 ?98/04 -36- sclk -serial clock, pin 62. (host mode) clock used to read or write the serial port registers. sclk can be either high or low when the line interface is selected using the cs pin. sdi -serial data input, pin 60. (host mode) data for the on-chip register. sampled on the rising edge of sclk. sdo -serial data output, pin 61. (host mode) status and control information from the on-chip register. if spol is high sdo is valid on the rising edge of sclk. if spol is low, sdo is valid on the falling edge of sclk. this pin goes to a high-impedance state when the serial port is being written to or after bit d7 is output. taos1,2 -transmit all ones select, pin 60, 59. (hardware mode) setting taos to a logic 1 causes continuous ones to be transmitted at the frequency determined by refclk. status ais1, ais2 -all ones signal detection, pins 6, 43. ais goes high when an all-ones condition is detected using the detection criteria of less than nine zeros out of 8192 bit periods. bpv1, bpv2 -bipolar violation detection, pins 3, 46. bpv goes to a logic 1 for one bit period when a bipolar violation is detected in the received signal. b8zs (or hdb3) zero substitutions are not flagged as bipolar violations if the b8zs (or hdb3) decoder has been enabled. los1, los2 -loss of signal, pins 7, 42. los goes to a logic 1 when 175 consecutive zeros have been detected. los returns to logic 0 when a 12.5% ones density signal returns. spol -sdo polarity control, pin 59. (host mode) setting spol to logic 1, causes sdo to be valid on the rising edge of sclk. setting spol to logic 0 causes sdo to be valid on the falling edge of sclk. reference clock 1xclk -one-times clock frequency select, pin 28. when 1xclk is set to logic 1, refclk should be a 1.544 mhz for t1 or 2.048 mhz for e1 applications. when 1xclk is set to logic 0, refclk should be an 8x clock, i.e., 12.352 mhz for t1 or 16.384 mhz for e1 applications. refclk -external reference clock input, pin 26. a reference clock for the receiver and jitter attenuator circuits of both channels. when 1xclk is set to logic 1, refclk should be 1.544 mhz for t1 or 2.048 mhz for e1 applications. when 1xclk is set to logic 0, refclk should be 12.352 mhz for t1 or 16.384 mhz for e1 applications.
asahi kasei [AK61584] 0185-e-00 ?98/04 -37- t1/e1 data inputs and outputs rclk1, rclk2 -receive clock, pins 1, 48. rpos1/rdata1, rpos2/rdata2 -receive positive data, pins 2, 47. rneg1, rneg2 -receive negative data, -pins 3, 46. the receiver recovered clock and nrz digital data is output on these pins. clke determines the clock edge for which rpos and rneg are stable and valid. see table 3. a positive pulse (with respect to ground) received on the rtip pin generates a logic 1 on rpos, and a positive pulse received on the rring pin generates a logic 1 on rneg. in coder mode, the decoded digital data stream is output on rdata. rtip1, rring1, rtip2, rring2 -receive tip, receive ring, pins 17, 18, 32, 31. the ami receive signal is input to these pins. step -down transformer is required on these inputs. data and clock are recovered and output on rpos/rneg (rdata) and rclk. tclk1, tclk2 -transmit clock, pin 4, 45. tpos1/tdata1, tpos2/tdata2 -transmit positive data, pins 5, 44. tneg1, tneg2 -transmit negative data, -pins 6, 43. inputs for clock and data to be transmitted. the signal is driven on to the line through ttip and tring. tpos and tneg are sampled on the falling edge of tclk. a tpos input causes a positive pulse to be transmitted, while a tneg input causes a negative pulse to be transmitted. in coder mode, the un-encoded digital data stream is input on tdata. ttip1, tring1, ttip2, tring2 -transmit tip, transmit ring, pins 11, 14, 38, 35. the ami signal is driven to the line through these pins. this output is designed to drive the primary of the recommended transformer. in transparent mode, tpos drives ttip, and tneg drives tring. in coder mode, tdata drives ttip and tring. test j_tclk-j tag test clock, pin 40. data on pins j_tdi and j_tdo in valid on the rising edge of j_tck. when j_tck in stopped low, all jtag registers remain unchanged. j_tms -j tag test mode select, pin 39. an active high signal on this pin enables the jtag serial port. connected to an internal pull -up resistor. j_tdi -j tag test data in, pin 10. jtag data is shifted into the AK61584 via this pin. connected to an internal pull-up resistor. data should be stable on the rising edge of j_clk. j_tdo -j tag test data out, pin 8. jtag data is shifted out of the AK61584 via this pin. this pin is active except when jtag testing is in progress. j_tdo will be updated on the falling edge of j_tck.
asahi kasei [AK61584] 0185-e-00 ?98/04 -38- marking (1) akm logo. (2) marketing code :AK61584 (3) date code :7digits xxxxxxx (4) country of origin :japan outline dimensions AK61584 xxxxxxx japan akm 12.00.3 10.0 0.2 0.15+0.05 10.0 12.00.3 1 16 17 32 33 48 49 64 0.5 0.1 m -0.03 1.4 0.2max 0.10 unit:mm 0- 10 1.0 0.50.1 1.7max

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